1. Field of the Invention
The invention relates to an electrode process. More particularly, the invention relates to a method for fabricating a bottom electrode of a capacitor.
2. Description of the Related Art
As the semiconductor technology being greatly developed, millions of transistors are formed on a chip. Such chip, belongs to an Ultra-Large-Scale Integrated (ULSI) generation, has a need of high speed and access memory capacitance. For this need, techniques of applying a material with a high dielectric constant as a capacitor dielectric layer are greatly developed. For example, a BST ((Ba, Sr)TiO.sub.3) dielectric material, which has a high dielectric constant and a low film leakage current, is broadly applied to dynamic random access memories (DRAMs) with 4G bits or more access capacitance. Moreover, a noble metal, such as platinum (Pt), is used as an electrode material of capacitors of such memories. Pt has many inherent advantages, such as a low leakage current, a high conductivity and an improvement in problem of a depletion region in a dual-polysilicon capacitor.
Referring to FIG. 1, a Pt electrode 108 is shown. The drawing further shows a substrate 100 with a doped area 106, a dielectric layer 102 having a contact 104, and a TiN barrier layer 110 over the contact 104.
The method of fabricating the Pt electrode 108 comprises a step of forming a Pt layer, followed by a photolithography and etching step. As shown in the figure, due to the difficulty in etching the Pt layer, surface area is reduced after being etched. As a consequence, the capacitance of a capacitor based on the Pt electrode 108 is reduced.